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Integrated Circuit Systems, Inc.
ICS95V2F857A
2.5V Wide Range Frequency Clock Driver (45MHz - 233MHz)
Recommended Application: * Heavy loaded/4 rank * DDR Memory Modules / Zero Delay Board Fan Out * Provides complete DDR registered DIMM solution with ICSSSTVF16857, ICSSSTVF16859 or ICSSSTVA32852 Product Description/Features: * Higher drive than the 95V857 series devices * Low skew, low jitter PLL clock driver * 1 to 10 differential clock distribution (SSTL_2) * Feedback pins for input to output synchronization * PD# for power management * Spread Spectrum-tolerant inputs * Auto PD when input signal removed Specifications: * Meets PC3200 Class A+ specification for DDR-I 400 support * Covers all DDRI speed grades Switching Characteristics: * CYCLE - CYCLE jitter: <50ps * OUTPUT - OUTPUT skew: <40ps * Period jitter: 30ps
Pin Configuration
GND CLKC0 CLKT0 VDD CLKT1 CLKC1 GND GND CLKC2 CLKT2 VDD VDD CLK_INT CLK_INC VDD AVDD AGND GND CLKC3 CLKT3 VDD CLKT4 CLKC4 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 GND CLKC5 CLKT5 VDD CLKT6 CLKC6 GND GND CLKC7 CLKT7 VDD PD# FB_INT FB_INC VDD FB_OUTC FB_OUTT GND CLKC8 CLKT8 VDD CLKT9 CLKC9 GND
48-Pin TSSOP/TVSOP
6.10 mm Body, 0.50 mm Pitch = TSSOP 4.40 mm Body, 0.40 mm Pitch = TVSOP
Block Diagram
FB_OUTT FB_OUTC
Functionality
INPUTS AVDD PD# GND GND 2.5V (nom) 2.5V (nom) 2.5V (nom) 2.5V (nom) 2.5V (nom) H H L L H H X CLK_INT L H L H L H <20MHz)(1) OUTPUTS PLL State CLK_INC CLKT CLKC FB_OUTT FB_OUTC H L H L H L L H Z Z L H Z H L Z Z H L Z L H Z Z L H Z H L Z Z H L Z Bypassed/off Bypassed/off
ICS95V2F857A
CLKT0 CLKC0 CLKT1 CLKC1
Control
off off on on off
PD#
Logic
CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4
FB_INT FB_INC CLK_INC CLK_INT
CLKT5 CLKC5
PLL
CLKT6 CLKC6 CLKT7 CLKC7 CLKT8 CLKC8 CLKT9 CLKC9
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ICS95V2F857A
Pin Configuration
1 A B C D E F G H J K 2 3 4 5 6
A B C D E F G H J K
1 CLKT0 CLKC1 GND CLKT2 VDD CLK_INT VDD AGND CLKC3 CLKT4
2 CLKC0 CLKT1 GND CLKC2 VDD CLK_INC AVDD GND CLKT3 CLKC4
3 GND VDD NC NC NB NB NC NC VDD GND
4 GND VDD NC NC NB NB NC NC VDD GND
5 6 CLKC5 CLKT5 CLKT6 CLKC6 GND GND CLKC7 CLKT7 VDD PD# FB_INC FB_INT FB_OUTC VDD GND FB_OUTT CLKT8 CLKC8 CLKC9 CLKT9
56-Ball BGA
CLKC1 CLKT1 VDD CLKT0 CLKC0 CLKC5 CLKT5 VDD CLKT6 CLKC6
40 31
GND CLKC2 CLKT2 VDD CLK_INT CLK_INC VDD AVDD AGND GND
1
30
ICS95V2F857A
10
21 11 20
CLKC7 CLKT7 VDD PD# FB_INT FB_INC VDD VDD FB_OUTC FB_OUTT
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CLKC3 CLKT3 VDD CLKT4 CLKC4 CLKC9 CLKT9 VDD CLKT8 CLKC8
40-Pin MLF
2
ICS95V2F857A
Pin Descriptions
PIN NAME VDD GND AVDD AGND CLKT(9:0) CLKC(9:0) CLK_INC CLK_INT FB_OUTC TYPE PWR PWR PWR PWR OUT OUT IN IN OUT Power supply, 2.5V Ground Analog power supply, 2.5V A n a l o g gr o u n d "Tr ue" Clock of differential pair outputs "Complementar y" clocks of differential pair outputs "Complementar y" reference clock input "True" reference clock input "Complementar y" Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INC "True" " Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INT "True" Feedback input, provides feedback signal to the internal PLL for synchronization with CLK_INT to eliminate phase error "Complementar y" Feedback input, provides signal to the internal PLL for synchronization with CLK_INC to eliminate phase error Power Down. LVCMOS input DESCRIPTION
FB_OUTT FB_INT FB_INC PD#
OUT IN IN IN
This PLL Clock Buffer is designed for a VDD of 2.5V, an AVDD of 2.5V and differential data input and output levels. The ICS95V2F857A is a zero delay buffer that distributes a differential clock input pair (CLK_INC, CLK_INT) to ten differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock output (FB_OUT, FB_OUTC). The clock outputs are controlled by the input clocks (CLK_INC, CLK_INT), the feedback clocks (FB_INT, FB_INC), the 2.5-V LVCMOS input (PD#) and the Analog Power input (AVDD). When input (PD#) is low while power is applied, the receivers are disabled, the PLL is turned off and the differential clock outputs are tri-stated. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When the input frequency is less than the operating frequency of the PLL, appproximately 20MHz, the device will enter a low power mode. An input frequency detection circuit on the differential inputs, independent from the input buffers, will detect the low frequency condition and perform the same low power features as when the (PD#) input is low. When the input frequency increases to greater than approximately 20 MHz, the PLL will be turned back on, the inputs and outputs will be enabled and PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INC, CLK_INT). The PLL to the ICS95V2F857A clock driver uses the input clocks (CLK_INC, CLK_INT) and the feedback clocks (FB_INT, FB_INC) provide high-performance, low-skew, low-jitter, output differential clocks (CLKT[0:9], CLKC[0:9]). The ICS95V2F857A is also able to track Spread Spectrum Clock (SSC) for reduced EMI. The ICS95V2F857A is characterized for operation from 0C to 85C, and will meet JEDEC Standard 82-1 and 82-1A Class A+ for registered DDR clock drivers.
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ICS95V2F857A
Absolute Maximum Ratings
Supply Voltage (VDD & AVDD) . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . -0.5V to 4.6V GND -0.5 V to V DD + 0.5 V 0C to +85C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5V 0.2V PARAMETER Input High Current Input Low Current Operating Supply Current Output High Current Output Low Current High Impedance Output Current Input Clamp Voltage High-level output voltage SYMBOL I IH I IL I DD2.5 I DDPD I OH I OL I OZ V IK CONDITIONS V I = VDD or GND V I = VDD or GND CL = 0pf @ 200MHz CL = 0pf V DD = 2.3V, VOUT = 1V V DD = 2.3V, VOUT = 1.2V V DD=2.7V, Vout=VDD or GND V DDQ = 2.3V Iin = -18mA V DD = min to max, I OH = -1 mA V DDQ = 2.3V, I OH = -12 mA V DD = min to max I OL=1 mA V DDQ = 2.3V I OH=12 mA V I = GND or V DD V OUT = GND or VDD VDDQ - 0.1 1.7 0.1 0.6 3 3 MIN 5 TYP MAX 5 175 100 UNITS A A mA A mA mA 10 -1.2 mA V V V V V pF pF
155 -18 26 -32 35
VOH
Low-level output voltage
VOL
Input Capacitance1 Output Capacitance1
1
CIN COUT
Guaranteed by design at 220MHz, not 100% tested in production.
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4
ICS95V2F857A
Recommended Operating Condition (see note1)
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) PARAMETER Supply Voltage Low level input voltage High level input voltage DC input signal voltage (note 2) Differential input signal voltage (note 3) Output differential crossvoltage (note 4) Input differential crossvoltage (note 4) High level output current Low level output current Operating free-air temperature SYMBOL V DD, A VDD VIL VIH VIN VID VOX VIX I OH I OL TA 0 DC - CLKT, FB_INT AC - CLKT, FB_INT CONDITIONS CLKT, CLKC, FB_INC PD# CLKT, CLKC, FB_INC PD# MIN 2.3 -0.3 VDD/2 + 0.18 1.7 -0.3 0.36 0.7 V DD/2 - 0.15 V DD/2 - 0.2 VDD/2 TYP 2.5 0.4 2.1 VDD + 0.6 VDD + 0.3 VDD + 0.6 VDD + 0.6 VDD/2 + 0.15 VDD/2 + 0.2 -30 -30 85 MAX 2.7 VDD/2 - 0.18 0.7 UNITS V V V V V V V V V V mA mA C
Notes: 1. Unused inputs must be held high or low to prevent them from floating. 2. DC input signal voltage specifies the allowable DC execution of differential input. 3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required for switching, where VT is the true input level and VCP is the complementary input level. 4. Differential cross-point voltage is expected to track variations of VDD and is the voltage at which the differential signal must be crossing.
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ICS95V2F857A
Timing Requirements
TA = 0 - 85C; Supply Voltage AVDD, V DD = 2.5 V +/- 0.2V (unless otherwise stated) CONDITIONS PARAMETER SYMBOL MIN MAX Max clock frequency Application Frequency Range Input clock duty cycle CLK stabilization freqop freqApp dtin TSTAB 2.5V+0.2V @ 25 C 2.5V+0.2V @ 25oC
o
UNITS MHz MHz % s
45 95 40
233 220 60 15
Switching Characteristics (see note 3)
PARAMETER Low-to high level propagation delay time High-to low level propagation delay time Output enable time Output disable time Period jitter Half-period jitter Input clock slew rate Output clock slew rate Cycle to Cycle Jitter1 Static Phase Offset Output to Output Skew SYMBOL t PLH1 t PLL1 t EN tdis Tjit (per) t(jit_hper) tsl(i) tsl(o) Tcyc -Tcyc t (static phase offset) Tskew
4
CONDITION CLK_IN to any output CLK_IN to any output PD# to any output PD# to any output 100MHz to 200MHz 100MHz to 200MHz
MIN
TYP 3.5 3.5 3 3
MAX
UNITS ns ns ns ns ps ps V/ns V/ns ps ps ps
100MHz to 200MHz
-30 -100 1 1 -50 -50
0
30 100 4 2 50 50 40
Notes: 1. Refers to transition on noninverting output in PLL bypass mode. 2. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle=twH/tc, where the cycle (tc) decreases as the frequency goes up. 3. Switching characteristics guaranteed for application frequency range. 4. Static phase offset shifted by design.
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ICS95V2F857A
Parameter Measurement Information VDD V(CLKC)
R = 60
R = 60 VDD/2 V(CLKC) ICS95V2F857A GND Figure 1. IBIS Model Output Load VDD/2 ICS95V2F857A Z = 60 C = 14 pF -V DD/2 Z = 50 SCOPE
R = 10
R = 50 V(TT) Z = 60 R = 10 Z = 50
C = 14 pF -VDD/2 -VDD/2 NOTE: V(TT) = GND Figure 2. Output Load Test Circuit
R = 50 V(TT)
YX, FB_OUTC YX, FB_OUTT tc(n) tc(n+1) tjit(cc) = tc(n) tc(n+1) Figure 3. Cycle-to-Cycle Jitter
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ICS95V2F857A
Parameter Measurement Information CLK_INC CLK_INT
FB_INC FB_INT
t( ) n
n=N t( ) n 1 t( )= N (N is a large number of samples) Figure 4. Static Phase Offset
t ( ) n+1
YX # YX
YX, FB_OUTC YX, FB_OUTT t(SK_O) Figure 5. Output Skew
YX, FB_OUTC YX, FB_OUTT YX, FB_OUTC YX, FB_OUTT 1 fO t(jit_per) = tC(n) - 1 fO Figure 6. Period Jitter
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ICS95V2F857A
Parameter Measurement Information YX, FB_OUTC YX, FB_OUTT
t (hper_n) 1 fo t (hper_n+1)
t(jit_Hper) = t(jit_Hper_n) - 1 2xfO Figure 7. Half-Period Jitter
80%
80% VID , VOD
Clock Inputs and Outputs
20% Rise tsl Fall tsl
20%
Figure 8. Input and Output Slew Rates
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ICS95V2F857A
N
c
L
INDEX AREA
E1
E
12 D
a
In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS a 0 8 0 8 aaa -0.10 -.004 VARIATIONS
A2 A1
A
-Ce
b SEATING PLANE
N 48
10-0039
D mm. MIN MAX 12.40 12.60
D (inch) MIN .488 MAX .496
Reference Doc.: JEDEC Publication 95, M O-153
aaa C
6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil)
Ordering Information
Example:
ICS95V2F857AG(LF)T ICS XXXX y G - (LF) - T
Designation for tape and reel packaging Lead Free (Optional) Package Type G = TSSOP Revision Designator (Ex. A, B, C, etc. Please check with salesperson for latest revision) Device Type Prefix ICS = Standard Device
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ICS95V2F857A
N
c
L
INDEX AREA
E1
E
12 D
In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.13 0.23 .005 .009 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 6.40 BASIC 0.252 BASIC E1 4.30 4.50 .169 .177 e 0.40 BASIC 0.016 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS a 0 8 0 8 aaa -0.08 -.003 VARIATIONS
A2 A1
A
-Ce
b SEATING PLANE
N 48
1 0-0037
D mm. MIN 9.60 MAX 9.80 MIN .378
D (inch) MAX .386
Reference Do c.: JEDEC P ublicatio n 95, M O-1 53
aaa C
4.40 mm. Body, 0.40 mm. pitch TSSOP (173 mil) (16 mil)
Ordering Information
Example:
ICS95V2F857AL(LF)T ICS XXXX y L - (LF) - T
Designation for tape and reel packaging Lead Free (Optional) Package Type L = TSSOP (TVSOP) Revision Designator (Ex. A, B, C, etc. Please check with salesperson for latest revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS = Standard Device
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ICS95V2F857A
Symbol A A1 A2 A3 D D1 E E1 Q P R e N Nd Ne L 0.30 0.18 0.00 2.75 2.75 0.24 0.13 0.00 -
Common Dimensions 0.85 0.01 0.65 0.20 REF 6.00 BSC 5.75 BSC 6.00 BSC 5.75 BSC 12 0.42 0.17 0.50 BSC 40 10 10 0.40 0.23 0.20 2.90 2.90 0.50 0.30 0.45 3.05 3.05 0.60 0.23 0.90 0.05 0.80
40-Pin MLF
Pitch Varation D
Ordering Information
Example:
b Q D2 E2
ICS95V2F857AK(LF)T ICS XXXX y K - (LF) - T
Designation for tape and reel packaging Lead Free (Optional) Package Type K = MLF Revision Designator (Ex. A, B, C, etc. Please check with salesperson for latest revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
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ICS95V2F857A
C Seating Plane A1 T b REF Numeric Designations for Horizontal Grid 4321 A B C D
D
Alpha Designations for Vertical Grid (Letters I, O, Q & S not used)
d TYP D1 - e - TYP TOP VIEW
E
h TYP 0.12 C
c REF E1
- e - TYP
ALL DIMENSIONS IN MILLIMETERS D 7.00 Bsc E 4.50 Bsc T Min/Max 0.8/1.00 e 0.65 Bsc ----- BALL GRID ----HORIZ VERT 6 10 Max. TOTAL 56 d Min/Max 0.3/0.45 h Min/Max 0.15/0.25 D1 5.85 Bsc E1 3.25 Bsc REF. DIMENSIONS b c 0.575 0.625 **
Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. * Source Ref.: JEDEC Publication 95, 10-0055 MO-205*, MO-225**
Ordering Information
Example:
ICS95V2F857AH(LF)T
ICS XXXX y H (LF) - T
Designation for tape and reel packaging Lead Free (optional) Package Type H = BGA Revision Designator (Ex. A, B, C, etc. Please check with salesperson for latest revision) Device Type Prefix ICS = Standard Device
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